Data applied to the input of this circuit is shifted one ceII to right following the clock pulse. The circuit is shown here. A shift register is formed by D-type flip-flops cascaded as sown in the figure. Each stage stores one bit of data. Data is applied to the input and shifted to right with the clock pulse. After a number of pulses equal to the number of stages, data applied in the input appears in the output. Data can also be available in the output of each stage. This kind of shift register that has a serial input for the signals and parallel outputs is also called SIPO [Serial In - Parallel out].
Shift Register Using the 4027
