Functional Diagram and/or Package:
Pin Names:
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Vdd - Positive Supply Voltage [5V to 15V]
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Vss – Ground
- Q1 /Q1I /, Q2/Q2/ Q3/Q3 / Q4/Q4/ - Outputs
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RST – Reset
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Clk'- Clock
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T/C - True Complement Input
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P/S - Parallel/Serial Selection
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J - Input Logic
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K - Input Logic
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P1, P2, P3, P4 - Parallel Inputs
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Truth Table:
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Operation Mode:
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a] Parallel Load Data
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- Data is applied to the inputs P1 to P4. P1 is nearest the input.
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- Next, LD must go the “'’” logic level.
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- In the next positive transition of the clock signal, data is loaded into the shift register.
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- LD must be kept in the “1” level until after clocking, and then it can drop.
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b] Serial ln/Serial Out or Serial In/Parallel Out
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- J and K are connected together.
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- TC, RST, and LD are also tied together.
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- Input data is applied to the J and K inputs. Data Will appear at the output D'l after a positive transition of the clock signal.
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- The second clock pulse transfers the signal to the next stage and so on.
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Electrical Characteristics:
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Applications:
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Counters
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Registers
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Serial-to-Parallel and Parallel-to-Serial Converters
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Shift/ Shift Right Registers
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Control Applications
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Code Conversion
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Sequence Generation
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Observations:
- The words applied to the inputs must arrive least significant bit first. A sign bit must follow the most significant bit.
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