This circuit divides frequencies of up to about 7 MHz by 10 and by 100. The input signal must be square, and the output signal is also rectangular, but the active cycle is not 50%. The power can be between 5 and 15 V. With lower voltages, the maximum input frequency is less than 7 MHz. The circuit is from the CMOS Sourcebook by Newton C. Braga, published in the United States.
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